USB3.1/3.0

USB is the ubiquitous peripheral-interconnect of choice for a large number of computing and consumer applications. Many Innosilicon systems provide a comprehensive set of software drivers to support commonly available USB peripherals. In addition, we have an existing USB ecosystem that includes USB silicon suppliers, design IP houses, and verification and testing vendors that lowers the cost for product manufacturers of USB hosts and peripherals.

USB3.1/3.0

USB3.1/3.0 PHY & Controller

The Innosilicon USB3.1/3.0 PHY is a highly programmable module that processes high-speed serial data into parallel data compatible with the PHY Interface for USB3.1/3.0 standard from Intel. The PHY supports USB3.0 SuperSpeed (5Gb/s) physical layer specifications.

Streamlined production testing is supported through BIST, multiple loopback modes, and boundary scan. Its modular nature is flexible, ensuring a PHY combination that is able to support the latest in C-type connector configurations while including all the I/Os and ESD in a single drop-in block. As with all Innosilicon IPs, our USB 3.0/3.1 solution is fully customizable to meet your specific needs.

Highlights
Features
Standard Deliverables
Example Applications

Small die size
Low pin counts
Low power consumption
Fully customizable
Supports 5.0Gb/s serial data transmission rate
Utilizes 8-bit, 16-bit or 32- bit parallel interface to transmit and receive USB SuperSpeed data
Allows integration of high speed components into a single functional block as seen by the device designer.
Data and clock recovery from serial stream on the USB SuperSpeed bus
Holding registers to stage transmit and receive data
Supports direct disparity control for use in transmitting compliance pattern
8b/10b encode/decode and error indication
Receiver detection
Low Frequency Periodic Signaling (LFPS) Transmission
Selectable Tx Margining
One PHY supports 3 protocols (shared PMA)

Reference Clock

25-300MHz, integer multiple of Serial output
+/-300ppm frequency stability (<20Gbps)
Supports both SRNS & SRIS modes
Configurable as reference clock repeater

Internal PLL

Used to drive all PHY transmitters and receivers
Ring PLL covering 1.0-5Gbps
Programmable pre-divider & feedback divider
Initiative SSC or reference clock based passive SSC
LOCK indication

Data Transmit

Rates supported from 1.0-5Gbps
AC coupled
50Ω impedance, internally calibrated
200-1000mV differential peak-peak, programmable
3 tap pre/post-cursor de-emphasis, programmable
Programmable Rise/Fall times

Data Receive

AC coupled
50Ω impedance, internally calibrated
200-1200mV differential peak-peak
CTLE, programmable
DFE, 6-tap programmable
CDR

Testing

Scan
BIST with PRBS7, PRBS23 and PRBS31(PG & SD)
Loopback (near-end, far-end, on/off-die)
On-chip scope (eye height & width)
Analog and digital probe points
HTOL
IDDQ

ESD

HBM 2000V, [JEDEC JS-001-2014]
MM 100V, [JEDEC JESD22-A115C]
CDM 250V, [JEDEC JESD22-C101F]

Latch Up

+-200mA for IO and 1.5*Vsupply for power rails

Package

Wire bond with careful SI/PI analysis for 8Gbps and below
Flip-Chip with careful SI/PI analysis for 8Gbps and up

Interface with controller

PIPE4.3 & 32 bits data bus for PCIe and USB3.x

Sim Behavioral simulation model for the PHY
Encrypted IO spice netlist for SI evaluation
Integration Guidelines
Test Guidelines
GDSII Layout and layer map for foundry merge
Place and Route LIB and LEF views for the AFE
LVS and DRC verification reports

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