eMMC/SD/SDIO

Innosilicon eMMC/SD/SDIO Combo IP solution consists of a host controller and PHY to supports eMMC/SD/SDIO devices. When connecting the eMMC device, the IP supports HS400, HS200, High-Speed DDR, High-Speed SDR, and legacy speed modes. When connecting the SD/SDIO device, the IP supports DS, HS, SDR12, SDR25, SDR50, SDR104, and DDR50 speed modes.

eMMC/SD/SDIO

The IP is fully compliant with the following standards: JESD84-B51 eMMC5.1 specifications, SD3.01 specifications, and SDIO3.00 specifications.

Highlights
Features
Standard Deliverables
Example Applications

High capacity
High speed
High compatibility

Compliant with eMMC5.1 specifications, up to 200MHz
Supports HS400, HS200, High-Speed DDR, High-Speed SDR, and back compatible with legacy eMMC interface
Supports Enhanced Strobe in HS400
Compliant with SD3.01/SDIO3.00 specifications, up to 208MHz
Supports DS, HS, SDR12, SDR25, SDR50, SDR104, and DDR50 speed mode
Supports adjusting the CMD/CLK/DAT IO Driver Strength
Supports power sequence-free operations
Supports open drain applications
ESD protection for I/O signal
Supports Built-In Self-Test
Supports VDDQ 3.3V/1.8V

Databook
Integration and Simulation Guide
Detailed physical implementation guides for the complete PHY
Library Exchange Format (LEF) file with pin size and locations
Gate-level netlist and Standard Delay Format (SDF)Timing file
Encrypted Verilog Models
Layout Versus Schematic (LVS) flattened netlist and report
Design Rule Check (DRC) report
GDSII database for foundry merge
Optional backend integration

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